This invention relates to a system for generating the control signals for phase-delay rectifiers, and more particularly to the use of combinational logic to implement gate firing control for phase-delay rectifiers which require a variable firing angle that ranges from near 0.degree. to near 180.degree..
In the speed control of a permanent magnet brushless motor, it is sometimes necessary to convert 3-phase power to direct current using a phase-delay rectifier (PDR) and then to change the direct current to alternating current using a line commutated inverter. The PDR is designed to provide a controlled current source for the line commutated inverter. The inverter provides the necessary 3-phase current to the motor windings and is synchronized with back emf by means of electronic switches.
The current to the motor is sensed to produce a signal that is compared with a current command signal; the difference is an error signal (.alpha.-control) applied to the PDR to produce a firing angle in a range from 0.degree. to 180.degree.. Any decrease from a desired motor speed results in a decrease in the PDR firing angle which in turn causes an increase in the PDR output voltage for increased current to the motor, and vice versa. This permits speed control of the motor by control of the current command signal.
The output voltage of a PDR is proportional to the cosine of the firing angle. Consequently, if a cosine ramp signal synchronized with the ac power phase is used in the generation of the firing angle, the output voltage becomes a linear function of the firing angle. For a given SCR relating to a given phase of a 3-phase PDR, this cosine ramp for each of the three power phases is a cosine waveform whose positive and negative maxima occur at the intersections of the other two phases. This ramp can thus be used to generate the SCR gate firing pulse. This is accomplished by comparing the .alpha.-control signal with the cosine ramp for the SCR to determine when cosine ramp exceeds the .alpha.-control signal to control the correct time for firing the SCR in a 3-phase bridge. In practice both positive and negative SCR devices are provided for a fullwave SCR bridge using a cosine ramp and both positive and negative .alpha.-control signals for the two SCRs associated with positive and negative half cycles of each power phase.
The prior art integrates the 3-phase line voltages and at the phase angle prescribed by a threshold comparator sets a flip-flop or triggers a one-shot to generate a firing signal. When the next phase reaches the threshold, its threshold comparator sets its flip-flop, or triggers its one shot, which at the same time resets the previously set flip-flop or one-shot. The problem with that prior-art arrangement is that a spurious noise signal can set a flip-flop, or trigger a one-shot. That could generate a firing signal prematurely, causing motor current and consequently motor speed to change spuriously.